Home Page People Projects Publications Funding Sources Awards / Recent News Job Openings Software WWW Carch UCY Carch Publications 2017 HARPA: Tackling Physically Induced Performance Variability Nikolaos Zompakis, Michail Noltsis, Lorena Ndreu, Zacharias Hadjilambrou, Panagiotis Englezakis, Panagiota Nikolaou, Antoni Portero, Simone Libutti, Giuseppe Massari, Federico Sassi, Alessandro Bacchini, Chrysostomos Nicopoulos, Yiannakis Sazeides, Radim Vavrik, Martin Golasowski, Jiri Sevcik, Vit Vondrak, Francky Catthoor, WIlliam Fornaciari and Dimitrios Soudris Design, Automation and Test in Europe, (DATE 2017), March 2017 BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers Davide Zoni, Andrea Canidio, William Fornaciari, Panayiotis Englezakis, Chrysostomos Nicopoulos, Yiannakis Sazeides Journal of Parallel and Distributed Computing, January 2017 How to make SMT Tail Latency Friendly Zacharias Hadjilambrou and Yiannakis Sazeides Energy-efficient Servers for Cloud and Edge Computing 2017 Workshop (ENeSCE 2017), HIPEAC 2017, January 2017 A Methodology for Oracle Selection of Monitors and Knobs for Configuring an HPC System running a Flood Management Application Panagiota Nikolaou, Yiannakis Sazeides, Antoni Portero, Radim Vavřík, Vit Vondrak 5th Workshop on High Performance Energy Efficient Embedded Systems (HIP3ES), HIPEAC 2017, January 2017 2016 Modeling the Implications of DRAM Failures and Protection Techniques on Datacenter TCO Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu and Marios Kleanthous ACACES 2016, July 2016 Shaving the Safety Margins by Exposing Intrinsic Hardware Heterogeneity Zacharias Hadjilambrou, Konstantinos Tovletoglou, Panagiota Nikolaou, Charalambos Chalios, Dimitrios Nikolopoulos, Pedro Trancoso, Yanos Sazeides and Georgios Karakonstantis ACACES 2016, July 2016 Toward Multi-Layer Holistic Evaluation of System Designs Marios Kleanthous, Yiannakis Sazeides, Emre Özer, Chrysostomos Nicopoulos, Panagiota Nikolaou, Zacharias Hadjilambrou Computer Architecture Letters, (CAL 2016), June 2016 An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures Kypros Chrysanthou, Panayiotis Englezakis, Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos, Yiannakis Sazeides, Giorgos Dimitrakopoulos ACM Transactions on Architecture and Code Optimization, (TACO 2016), April 2016 Approximating Standard Cell Delay Distributions by Reformulating the Most Probable Failure Point Dimitrios Rodopoulos, Philippe Roussel, Francky Catthoor, Yiannakis Sazeides, Dimitrios Soudris Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, ERMAVSS 2016, co-located with IEEE/ACM Design, Automation and Test in Europe Conference, (ERMAVSS@DATE 2016), March 2016 Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults Damien Hardy, Isabelle Puaut, Yiannakis Sazeides Design, Automation and Test in Europe, (DATE 2016), March 2016 Harnessing performance variability using intra-server partitioning for Web-Search Zacharias Hadjilambrou, Yiannakis Sazeides HiPEAC 2016, January 2016 2015 Modeling the Implications of DRAM Failures and Protection Techniques on Datacenter TCO Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu, Marios Kleanthous 48th Annual IEEE/ACM International Symposium on Microarchitecture, (MICRO48), December 2015 Toward Multi-Layer Holistic Evaluation of System Designs M. Kleanthous, Y. Sazeides, E. Ozer, C. Nicopoulos, P. Nikolaou and Z. Hadjilambrou IEEE Computer Architecture Letters Evaluation of intra-server partitioning for Web Search Zacharias Hadjilambrou and Yiannakis Sazeides, ACACES 2015, July 2015 Emulate the Performance Degradation due to Faults in Real Hardware using 'Degradation Bubble Framework' Lorena Ndreu and Yiannakis Sazeides, ACACES 2015, July 2015 Characterization and analysis of a web search benchmark Z. Hadjilambrou, Master Thesis, May 2015 Sensitivity of SRAM Cell Most Probable SNM Failure Point to Time-Dependent Variability D. Rodopoulos, Y. Sazeides, F. Catthoor, C. Nicopoulos and D. Soudris The 11th Workshop on Silicon Errors in Logic - System Effects (SELSE-11), March 2015 The Implications of Different DRAM Protection Techniques on Datacenter TCO P. Nikolaou, Y. Sazeides, M. Kleanthous and L. Ndreu The 11th Workshop on Silicon Errors in Logic - System Effects (SELSE-11), March 2015 Characterization and Analysis of a Web Search Benchmark - Z. Hadjilambrou, M. Kleanthous and Y. Sazeides IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015), March 2015 2014 An Analytical Framework for Estimating TCO and Exploring Data Center Design Space - D. Hardy, M. Kleanthous, I. Sideris, A. Saidi, E. Ozer and Y. Sazeides IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2013) Edited version of the paper appeared at ISPASS 2013, February 2014 A Data Processing Apparatus Using Implicit Data Storage and a Method of Implicit Data Storage Y. Sazeides, E. Ozer, D. Kershaw and J. B. Brelot Publication number: US8694862 B2 Publication date: 8 Apr 2014 A Data Processing Apparatus and Method for Analyzing Transient Faults Occurring Within Storage Elements of the Data Processing Apparatus E. Ozer, Y. Sazeides, D. Kershaw and S. D. Biles Publication number: US8732523 B2 Publication date: 20 May 2014 Implicit-Storing and Redundant-Encoding-of-Attribute Information in Error-Correction-Codes Yiannakis Sazeides, Emre Ozer, Danny Kershaw, Panagiota Nikolaou, Marios Kleanthous, Jaume Abella, ACACES 2014, July 2014 2013 Modelling the impact of permanent faults in caches D. Sanchez, Y. Sazeides, J.M. Cebrian and J.L. Aragon, ACM TACO, 2013 Implicit-Storing and Redundant-Encoding-of-Attribute Information in Error-Correction-Codes - Y. Sazeides, E. Ozer, D. Kershaw, P. Nikolaou, M. Kleanthous, J. Abella 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO46), December 2013 Memory Array Protection:Check On Reads or Check On Writes? Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu, Emre Ozer and Sachin Idgunji, ACACES 2013, July 2013 Memory Array Protection: Check on Read or Check on Write? - P. Nikolaou, Y. Sazeides, L. Ndreu, E. Ozer and S. Idgunji Design, Automation and Test in Europe 2013 (DATE 2013), March 2013 2012 NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures - A. Prodromou, A. Panteli, C. Nicopoulos and Yannakis Sazeides 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO45), December 2012 The Performance Vulnerability of Architectural and non-Architectural Arrays to Permanent Faults - D. Hardy, I. Sideris, N. Ladas and Y. Sazeides 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO45), December 2012 Optimizing Data-Center TCO with Scale-Out Processors - B. Grot, D. Hardy, P. Lotfi-Kamran, B. Falsafi, C. Nicopoulos and Y. Sazeides IEEE Micro, Volume 32 (5), Pages 52-63, September - October 2012 Thermal Characterization of Cloud Workloads on a Low-power Server-on-Chip - D. Milojevic, S. Idgunji, D. Jevdjic, E. Ozer, P. Lotfi-Kamran, A. Panteli, A. Prodromou, C. Nicopoulos, D. Hardy, B. Falsafi and Y. Sazeides 30th IEEE International Conference on Computer Design (ICCD), September 2012 Cache Content Duplication - M. Kleanthous, PhD Thesis, April 2012 Redundant Encoding of Attributes in Error Correction Codes - Y. Sazeides, D. Kerhsaw and E. Ozer IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2012 2011 EETCO: a tool to Estimate and Explore the implications of datacenter design choices on the TCO and the environmental impact - D. Hardy, I. Sideris, A. Saidi and Y. Sazeides Workshop on Energy-efficient Computing for a Sustainable World (held in conjunction with MICRO44), December 2011 CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication in Instruction Caches - M. Kleanthous and Y.Sazeides ACM Trans. Archit. Code Optim., Volume 8 (3), Pages 11:1-11:27, October 2011 Eliminating Energy of Same-Content-Cell-Columns of On-Chip SRAM Arrays - Bushra Ahsan, Lorena Ndreu, Isidoros Sideris, Yiannakis Sazeides, Sachin Idgunji and Emre Ozer International Symposium on Low Power Electronics and Design 2011, Fukuoka, Japan, August 1-3, 2011 A Count-Based Scheme for Fault Detection in Memory Arrays Lorena Ndreu, Yiannakis Sazeides, Bushra Ahsan, and Isidoros Sideris, ACACES 2011, July 2011 An Analytical Model for the Calculation of the Expected Miss Ratio in Faulty Caches - Daniel Sanchez, Yiannakis Sazeides, Juan L. Aragon, Jose M. Garcõa IEEE International On-Line Testing Symposium, Athens, Greece, July 13-15 2011 RVC-Based Time-Predictable Faulty Caches for Safety-Critical Systems - Jaume Abella, Eduardo Quinones, Francisco J. Cazorla, Yanos Sazeides, Mateo Valero IEEE International On-Line Testing Symposium, Athens, Greece, July 13-15 2011 CBFD: A Count-Based Fault Detection Scheme for Memory Arrays - Yiannakis Sazeides, Bushra Ahsan, Isidoros Sideris, Lorena Ndreu, Sachin Idgunji and Emre Ozer Silicon Errors in Logic - System Effects (SELSE) 2011 University of Illinois, United States, March 29-30, 2011 RVC: A Mechanism for Time-Analyzable Real-Time Processors with Faulty Caches - Jaume Abella, Eduardo Quinones, Francisco J. Cazorla, Yanos Sazeides and Mateo Valero 6th International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2011) Heraklion, Crete (Greece), January 24-26, 2011 Improving Branch Prediction by Considering Affectors and Affectees Correlations - Y.Sazeides, A. Moustakas, K. Constantinides, M. Kleanthous Transactions on HiPEAC: 3(1):69-88, 2011 2010 EuroCloud: Energy-conscious 3D Server-on-Chip for Green Cloud Services (Poster) - Emre Ozer, Krisztian Flautner, Sachin Idgunji, Ali Saidi, Yiannakis Sazeides, Bushra Ahsan, Nikolas Ladas, Chrysostomos Nicopoulos, Isidoros Sideris, Babak Falsafi, Almutaz Adileh, Michael Ferdman, Pejman Lotfi-Kamran, Mika Kuulusa, Pol Marchal and Nikolas Minas 2nd Workshop on Architectural Concerns in Large Datacenters (held in conjunction with ISCA-37), Saint-Malo, France, June 19, 2010 Extrinsic and Intrinsic Text Cloning - Marios Kleanthous, Yiannakis Sazeides and Marios D. Dikaiakos WIOSCA 2010 Workshop (held in conjunction with ISCA-37), Saint-Malo, France, June 19, 2010 Proposition for a Sequential Accelerator in Future General-Purpose Manycore Processors and the Problem of Migration-Induced Caches Misses - P. Michaud, Y. Sazeides, A. Seznec ACM International Conference on Computing Frontiers (CF), Bertinoro, Italy, May 17-19, 2010 Performance Effective Operation below Vcc-min - N. Ladas, Y. Sazeides, and V. Desmet IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), White Plains, NY, March 2010 Performance Implications of Faults in Prediction Arrays - N. Ladas, Y. Sazeides, and V. Desmet 2nd HiPEAC Workshop on Design for Reliability (DFR 2010), Pisa, Italy, January 2010 2009 Proposition for a sequential accelerator in future general-purpose manycore processors - P. Michaud, Y. Sazeides, A. Seznec, INRIA report RR-7106, November 2009 Protecting Prediction Arrays Against Faults - Y. Sazeides, C. Kourouyiannis, N. Ladas, and V. Desmet IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), Stanford University, USA, March 2009 2008 Mitigating the Performance Degradation due to Faults in Non-Architectural Structures C. Kourouyiannis, Y. Sazeides, and V. Desmet 6th International Conference on High Performance Embedded Architectures and Compilers (HiPEAC) Industrial Workshop, Paris, France, November 2008 Thermal Aware Migration Techniques Christiana Ioannou, Yiannakis Sazeides, and Pierre Michaud, ACACES 2008, July 2008 CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches- M. Kleanthous and Y. Sazeides Design, Automation and Test in Europe (DATE), Munich, Germany, March 2008 The Significance of Affectors and Affectees Correlations for Branch Predicion - Y. Sazeides, A. Moustakas, K. Constantinides, and M. Kleanthous International Conference on High Performance Embedded Architectures and Compilers (HiPEAC), January 2008 2007 Performance Implications of Hard-Faults in Non-Architectural Structures V.Desmet, Y. Sazeides, and C. Vrionis Second Annual Recofingurable and Adaptive Architecture Workshop (RAAW-2), Chicago, USA (Dec. 2007) Initial Results on the Importance of Protecting Prediction Arrays Against Hard-Faults - V.Desmet, Y. Sazeides, and C. Vrionis 4th HiPEAC Industrial Workshop, Cambridge, UK (Nov. 2007) Using Grid for Micro-Architecture Research Liqiang He, Christiana Ioannou, Marios Kleanthous, and Yiannakis Sazeides, EGEE 2007, October 2007 Thermal Aware Multi-Core Scheduler Christiana Ioannou, Yiannakis Sazeides, Pierre Michaud and Martha Vasiliadou, ACACES 2007, July 2007 A Replacement Policy Based on Dynamic Profiling and Hashed Data Marios Kleanthous, Sami Yehia, Yiannakis Sazeides and Emre Ozer, ACACES 2007, July 2007 A study of thread migration in temperature-constrained multi-cores - P. Michaud, Y. Sazeides, A. Seznec, T. Constantinou and D. Fetis ACM Transactions on Architecture and Code Optimization, June 2007 ATMI: Analytical Model of Temperature in Microprocessors - P. Michaud and Y. Sazeides Third Annual Workshop on Modeling, Benchmarking and Simulation (MoBS), June 2007 Initial Results on the Performance Implications of Thread Migration on a Chip Multi-Core - Y. Sazeides, P. Michaud, L. He, D. Fetis, C. Ioannou, P. Charalambous and A. Seznec 3rd HiPEAC Industrial Workshop, Haifa, Israel , April 2007 Talk Dynamically Detecting Cache-Content-Duplication in Instruction Caches - M. Kleanthous, Y. Sazeides, TR-CS-03-2007, February 2007 2006 Cache-Content-Duplication for Valid Blocks Marios Kleanthous and Yiannakis Sazeides, ACACES 2006, July 2006 Characterizing Cache-Content-Duplication and Its Applications to Instruction Caches - M. Kleanthous, Master Thesis, June 2006 2005 Performance Implications of Single Thread Migration on a Chip Multi-Core * - Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, and Andre Seznec Computer Architecture News, Volume 33 , Issue 4 (November 2005) * This work is an extension of the work that appeared in dasCMP 2005 (Micro-38), November 2005 An analytical model of temperature in microprocessors - P. Michaud, Y. Sazeides, A. Seznec, T. Constantinou, D. Fetis, November 2005, IRISA report PI-1760 and INRIA report RR-5744 CATCH: A method for Dynamically Detecting Cache-Content-Duplication Marios Kleanthous and Yiannakis Sazeides, ACACES 2005, July 2005 Correct Alignment of a Return-Address-Stack after Call and Return Mispredictions - Veerle Desmet, Yiannakis Sazeides, Constantinos Kourouyiannis and Koen De Bosschere, 4th WDDD (ISCA-32), June 2005 Data Speculation - Y. Sazeides, P. Marcuello, J. Smith and A. Gonzalez, Book chapter in "Speculative Execution in High performance Computer Architecture" by CRC press. April 2005 The Danger of Interval Based Power Efficiency Metrics: When Worst is Best - Y. Sazeides, R. Kumar, D. Tullsen, T. Constantinou, in Computer Architecture Letters, Jan. 2005 The Duplication of Content in Instruction Caches and its Performance Implications - M. Kleanthous, Y. Sazeides, TR-CS-01-2005, Jan. 2005 2004 A Hardware Based Method for Dynamically Detecting Instruction Isomorphism and its Application to Branch Prediction - K. Constantinidis, Y. Sazeides, 2nd Value Prediction Workshop (affiliated with ASPLOSX), Oct. 2004 Microarchitectural Mechanisms for Performance-Efficient Energy Reduction & Instruction-Isomorphism in Program Execution - Y. Sazeides, 9th Intel Academic Forum, April 2004 2003 Adaptive Confidence Estimation - M. Patsalou, Master Thesis, December 2003 Instruction-Isomorphism in Program Execution - Y. Sazeides, JILP vol. 5 November 2003 The Isomorphism of Dynamic Conditional Branch Instructions - Y. Sazeides, TR-CS-03-2003, Nov. 2003 Selecting Long Atomic Traces - R. Rosner, M. Micha, Y. Sazeides, R. Ronen, ICS-17 June 2003 The Isomorphism of Instructions During Program Execution - Y. Sazeides, VPW1 (affiliated with ISCA-30) May 2003 (selected for journal publication) 2002 The Predictability of MPI messages - P. Panayiotou, Y. Sazeides and S. Evripidou, Dept. of Computer Science, University of Cyprus UCY-CS-TR01, November 2002 Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor - A. Seznec, S. Felix, V. Krishan, Y. Sazeides, ISCA-29 May 2002 Modeling Value Speculation - Y. Sazeides, HPCA-8 February 2002 Dependence Based Value Prediction - Y. Sazeides, Dept. of Computer Science, University of Cyprus, UCY-CS-TR00, Feb. 2002 2001 How to Compare the Performance of Two SMT microarchitectures - Y. Sazeides, and T. Juan, ISPASS 2001 November 2001 1999 Limits of Data Value Predictability - Y. Sazeides, and J. E. Smith, IJPP vol. 27 August 1999 An Analysis of Value Predictability and its Application to a Superscalar Processor - Y. Sazeides, Ph. D. Thesis, University of Wisconsin-Madison, February 1999 1998 Modeling Program Predictability - Y. Sazeides, and J. E. Smith, ISCA-25 May 1998 1997 The Predictability of Data Values - Y. Sazeides, and J. E. Smith, Micro-30 November 1997 Trace Processors - E. Rotenberg, Q. Jacobson, Y. Sazeides, and J. E. Smith, Micro-30 November 1997 (best paper award) Implementations of Context-Based Value Predictors - Y. Sazeides, and J. E. Smith, University of Wisconsin-Madison, TR ECE97-8 1996 The Performance Potential of Data Dependence Speculation and Collapsing - Y. Sazeides, S. Vassiliadis and J. E. Smith, Micro-29 November 1996 Contact the webmaster for any comments and suggestions