WDA-3 2008

3rd Workshop on Dependable Architectures
(extends previously held Workshop on Architectural Reliability - WAR)

In conjunction with the

41st International Symposium on Microarchitecture (MICRO-41)

Saturday, November 8, 2008
Lake Como, Italy

Workshop Proceedings

WDA-3 Program

8:30-9:30 Opening Session
Welcome and Outline
What to do with 100 Billion potentially misbehaving transistors on a chip Slides
Babak Falsafi, EPFL
9:30-10:00 Session I
Reducing Fault Detection Latencies in Virtually-Lockstepped Systems
Casey Jeffery and Renato J. O. Figueiredo (University of Florida)
10.00-10.30 Break
10.30-12.00 Session II
Automatic Adjustment of System Performance to Mitigate Device Aging via a Co-designed Virtual Machine
Omer Khan and Sandip Kundu (University of Massachusetts Amherst)
Exploiting Value Prediction for Fault Tolerance
Xuanhua Li and Donald Yeung (University of Maryland)
Multicore Power Management: Ensuring Robustness via Early-Stage Formal Verification
Anita Lungu (Duke), Pradip Bose (IBM), Dan Sorin (Duke), Steven German (IBM), and Geert Janssen (IBM)
Concluding Remarks


Current computer technology trends present to the hardware and software designer novel opportunities to improve performance and at the same time many challenges to overcome. One of the formidable challenges is to provide dependable operation - in terms of reliability and availability - for a system made of unreliable components.

The combination of various developments brought dependability to prominence: soft-error rate is projected to increase with scaling; variability due to non-deterministic placement of dopant atoms and channel length is increasing design margins; better than worst-case design techniques for power/performance require error detection/correction; aggressive application of power-saving mechanisms such as clock- and Vdd-gating are increasing voltage droops; the verification manpower budget is becoming a significant part of the design effort; oxide breakdown and electromigration are decreasing processor lifetimes.

New research frontiers are therefore open for exploration that will lead to the discovery and development of dependable architectures, this includes research at all design levels: circuit, architecture, compiler, OS and network. This workshop aims to become a forum for academia and industry to discuss and present ideas and recent developments in the design and evaluation of dependable architectures both software and hardware.

Call for papers:

Two kinds of papers are invited:
1. Technical papers (at least 6 pages) for relatively mature ideas.
2. Position papers (3 pages maximum) on directions for research and development.

Please submit an electronic copy of your paper (in PDF) in two column format with at least 10pt font.

SUBMIT PAPER Deadline has been extended until Friday, September 12th (11.59PM PDT)

The selected papers will be made available online. However, publication in WDA does not preclude later publication at regular conferences or journals.

Topics of interest include but not limited:

Important Dates

Paper due: September 12, 2008 (11.59PM PDT)
Notification: October 6, 2008
Final paper due: October 13, 2008


Yiannakis Sazeides, University of Cyprus
Osman Unsal, Barcelona Supercomputing Center
Oguz Ergin, TOBB University of Economic and Technology

Program Committee

Todd Austin, University of Michigan
David Brooks, Harvard University
Veerle Desmet, Ghent University
Oguz Ergin, TOBB University of Economic and Technology
Babak Falsafi, EPFL
C. Mani Krishna, UMass, Amherst
Shubu Mukherjee, Intel
Onur Mutlu, Microsoft
Jude Rivers, IBM
Yiannakis Sazeides, University of Cyprus
Osman Unsal, Barcelona Supercomputing Center
Xavi Vera, Intel
David Kaeli, Northeastern University

Previous Workshops

WAR-1 (2005)
WAR-2 (2006)

Constantinos Kourouyiannis, University of Cyprus