3rd Workshop on Dependable Architectures
(extends previously held Workshop on Architectural Reliability - WAR)
In conjunction with the
41st International Symposium on Microarchitecture (MICRO-41)
Saturday, November 8, 2008
Lake Como, Italy
|Welcome and Outline|
|What to do with 100 Billion potentially misbehaving transistors on a chip Slides|
|Babak Falsafi, EPFL|
|Reducing Fault Detection Latencies in Virtually-Lockstepped Systems|
|Casey Jeffery and Renato J. O. Figueiredo (University of Florida)|
|Automatic Adjustment of System Performance to Mitigate Device Aging via a Co-designed Virtual Machine|
|Omer Khan and Sandip Kundu (University of Massachusetts Amherst)|
|Exploiting Value Prediction for Fault Tolerance|
|Xuanhua Li and Donald Yeung (University of Maryland)|
|Multicore Power Management: Ensuring Robustness via Early-Stage Formal Verification|
|Anita Lungu (Duke), Pradip Bose (IBM), Dan Sorin (Duke), Steven German (IBM), and Geert Janssen (IBM)|
Current computer technology trends present to the hardware and software designer novel opportunities to improve performance and at the same time many challenges to overcome. One of the formidable challenges is to provide dependable operation - in terms of reliability and availability - for a system made of unreliable components.
The combination of various developments brought dependability to prominence: soft-error rate is projected to increase with scaling; variability due to non-deterministic placement of dopant atoms and channel length is increasing design margins; better than worst-case design techniques for power/performance require error detection/correction; aggressive application of power-saving mechanisms such as clock- and Vdd-gating are increasing voltage droops; the verification manpower budget is becoming a significant part of the design effort; oxide breakdown and electromigration are decreasing processor lifetimes.
New research frontiers are therefore open for exploration that will lead to the discovery and development of dependable architectures, this includes research at all design levels: circuit, architecture, compiler, OS and network. This workshop aims to become a forum for academia and industry to discuss and present ideas and recent developments in the design and evaluation of dependable architectures both software and hardware.
Call for papers:Two kinds of papers are invited:
Please submit an electronic copy of your paper (in PDF) in two column format with at least 10pt font.
SUBMIT PAPER Deadline has been extended until Friday, September 12th (11.59PM PDT)
The selected papers will be made available online. However, publication in WDA does not preclude later publication at regular conferences or journals.
Topics of interest include but not limited:
Important DatesPaper due: September 12, 2008 (11.59PM PDT)
Co-OrganizersYiannakis Sazeides, University of Cyprus
Program CommitteeTodd Austin, University of Michigan
Previous WorkshopsWAR-1 (2005)