CS Colloquium Series @ UCY

Department of Computer Science - University of Cyprus

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Colloquium Coordinator: Demetris Zeinalipour

Colloquium: Dynamic Voltage Frequency Scaling in Networks-on-Chip: use it without abuse it, Dr. Davide Zoni (Politecnico di Milano, Italy), Thursday, April 23, 2015, 15:00-16:00 EET.

The Department of Computer Science at the University of Cyprus cordially invites you to the Colloquium entitled:

Dynamic Voltage Frequency Scaling in Networks-on-Chip: use it without abuse it


Speaker: Dr. Davide Zoni
Affiliation: Politecnico di Milano, Italy
Category: Colloquium
Location: Room 148, Faculty of Pure and Applied Sciences (FST-01), 1 University Avenue, 2109 Nicosia, Cyprus (directions)
Date: Thursday, April 23, 2015
Time: 15:00-16:00 EET
Host: Yanos Sazeides (yanos-AT-cs.ucy.ac.cy)
URL: https://www.cs.ucy.ac.cy/colloquium/index.php?speaker=cs.ucy.2015.zoni

Network-on-Chip (NoC) is a flexible and scalable solution to interconnect multi-cores, with a strong influence on the performance of the whole chip. Furthermore, it affects the overall power consumption, thus early-stage estimation and optimization methodologies are required. In this scenario, the Dynamic Voltage Frequency Scaling (DVFS), traditionally exploited in CPUs, has been employed for the NoCs as well providing a flexible and scalable way to jointly optimize power-performance, addressing both static and dynamic power sources. Being simulation a de-facto prime solution to explore novel multi-core architectures, an holistic analysis requires to integrate accurate timing and power models for the DVFS block and for the resynchronization logic between different Voltage and Frequency Islands (VFIs). In such a way, a more accurate validation of novel optimization methodologies which exploit such actuator is possible, since both architectural and actuator aspects are considered at the same time. The talk focuses on the exploration of the use of the DVFS actuator in the NoC with particular emphasis on the impact of physical latencies due to the voltage regulator and the resynchronization schemes. Results are extracted from a full system cycle accurate simulator for multi-core supporting Global Asynchronous Local Synchronous (GALS) and DVFS actuators for the NoC. The proposed framework sits on accurate analytical timing model and SPICE-based power measures, providing accurate estimates of both timing and worst case power overheads of the actuator.

Short Bio:
Davide Zoni received the Master Degree in Computer Engineering from Politecnico di Milano in 2010 and the Ph.D. degree in Information Technology from Politecnico di Milano in 2014. He currently holds a Post-Doc position at the Dipartimento di Elettronica Informazione e Bioingegneria (DEIB), Politecnico di Milano, Italy. His main research interests include Networks-on-Chip, computer architecture as well as the application of control theory methodologies for power, performance and reliability optimizations in multi-cores. He received a best paper award in 2012 and two HiPEAC Collaboration Grants in 2013 and 2014.

The colloquium is jointly organized by the Department of Computer Science at the University of Cyprus and the Department of Electrical and Computer Engineering at the University of Cyprus.

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Sponsor: The CS Colloquium Series is supported by a generous donation from Microsoft