CS Colloquium Series @ UCY
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Colloquium Coordinator: Demetris Zeinalipour
Colloquium: A Routerless System-Level-Interconnect for Large Scale Multicore Systems, Prof. Donald M. Chiarulli (University of Pittsburgh, USA), Friday, June 5th, 2009, 11:00-12:00 EET.
The Department of Computer Science at the University of Cyprus cordially invites you to the Colloquium entitled:
A Routerless System-Level-Interconnect for Large Scale Multicore Systems
Speaker: Prof. Donald M. Chiarulli
This research is aimed at the development of a new interconnection network and control architecture for large-scale multi-core processors. It is designed to operate efficiently in systems with hundreds to thousands of active processor cores and provides a fully interconnected topology. Multiple programming models including symmetric common memory architectures are directly supported without significant restrictions imposed by the underlying network. Our specific focus is on a innovative set of design paradigms for these systems that are adaptable to both current CMOS electronic interconnection technology as well future silicon-optics technology. There are two fundamental ideas behind these paradigms. First, in designing both the physical interconnection network and the control algorithms, we endeavor to migrate complexity to the edges of network. This means that there will be little or no intelligence or routing capability in the network core. Instead, the physical interconnection network model is a simple many-to-many bus-style interconnection with distributed routing and access control decisions made exclusively the node interfaces. To make the network scalable, the strategy is to partition the network into sub-nets with multiple transceivers, one per subnet at each node interface. Each subnet connects the transmitters for all of the nodes in one partition to the receivers at all of the nodes in one other. The second fundamental idea is the basis of the scalable control architecture. Once again, our criterion is that all routing and control decisions must be fully distributed across nodes at the edges of the network. However, since there are no scalable solutions that can provide the global information at the timescale of individual bus transactions, bus access at this level is governed using a simple greedy algorithm. Each node claims a bus transaction on demand without regard to any pending claims by other nodes. When conflicts occur, a hardware encoded fixed rule, such as physical ordering on the bus, determines the winner. On a second level, in a time base spanning multiple transactions, a negative feedback mechanism is used to throttle the greedy algorithm at each node. When a node anticipates bus activity, it broadcasts a negative feedback message to all nodes. At every active node, the amount of negative feedback present limits the level of greed. At the time scale of this control algorithm, network bandwidth is near optimally allocated with a small percentage reserved to allow non-active nodes to initiate. Both levels allow for a great deal of flexibility. Overall bandwidth can allocated on a per node basis in the first level, by locally adjusting the strength of feedback. The second level control algorithm can operate on a demand basis or it can be made predicative by modeling software behavior or linkage to cache management algorithms.
Donald M. Chiarulli is a Professor of Computer Science and Computer Engineering at the University of Pittsburgh. He received his M.S. degree in Computer Science from the Virginia Polytechnic Institute and his Ph.D. also in Computer Science from Louisiana State University. Dr. Chiarulli's research interests are in Computer Architecture and are specifically focused on the application of novel technology to interconnection networks, system packaging, and mixed technology integration. Contributions from Dr. Chiarulli's group have included the demonstration of the first all-optical address decoder and several designs for time/space multiplexed data bus architectures. Recent contributions include the Partitioned Optical Passive Star (POPS) architecture for multiprocessor interconnection networks and the Multi Bit Differential Signaling (MBDS) methodology. Dr. Chiarulli has authored or co-authored over 40 technical papers including two that earned best paper awards at the International Conference on Neural Networks (ICNN) and the Design Automation Conference (DAC) respectively. Dr. Chiarulli is a member of the IEEE, and the SPIE.
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