|This project will be carried out in three main phases.
Phase 1: How fast a MWMR read/write operation can be?
During this phase we will explore whether operation latency efficient
algorithms that implement robust atomic registers in the MWMR model are
possible. The investigation will include two stages:
(a) a study of the efficiency limitations inherently imposed by the MWMR model, and
(b) adaptation of prior and introduction of new techniques to enable and support the development of
new algorithms that implement atomic R/W registers in the MWMR model with low operation latency.
Phase 2: Simulate our algorithms on a single processor simulation environments
During the 2nd phase, the algorithms proposed will be implemented in
single processor network simulators. Such simulators provide a
controlled testing environment. This will allow us to test the
performance of our algorithms under specific enviromental adversarial
Phase 3: Testing on real-time planetary scale environments.
For the last part of our project we plan to
implement and run our algorithms in planetary-scale real-environment
multitier networks. This will help us evaluate the efficiency and
practicality of our algorithms in real-time environments. In addition
this will evaluate the scalability of the proposed approaches and the
promise for more practical and reliable Distributed Storage Systems
with provable guarantees.