Kyriakos Stavrou (TSIK)
Research
The CASPER group
University Of Cyprus









  High-Performance Chip-Multiprocessor using Data Driven Multithreading (DDM) Architecture and Conventional Microprocessors Top  
    Abstract  
   
Data Driven Multithreading architecture is a multiprocessor system that schedules threads based on data availability. It allows for better performance through latency hiding at the expense of extra hardware. Although the potential of the proposed architecture has already been proved, this research focuses on the extensions of this architecture and its application to a chip-multiprocessor setup. Therefore, its speedup needs to be quantified it and compared to the last high-end microprocessors of equal hardware budget. Some parts of the architecture, such as the interconnection network and the TSU (Thread Scheduling Unit), deserve further study as we believe that improving their implementation will have a positive impact on performance.
 
    Publications  
   
Kyriakos Stavrou, Costas Kyriacou, Paraskevas Evripidou and Pedro Trancoso. "Chip Multiprocessor Based on Data-Driven Multithreading Model". International Journal of High Performance Systems Architecture. Volume 1 - Number 1 2007. In Press.
 
   
Pedro Trancoso, Paraskevas Evripidou, Kyriakos Stavrou, and Costas Kyriacou. "A Case for Chip Multiprocessors based on the Data-Driven Multithreading Model". International Journal of Parallel Programming. Volume 34 - Number 3. June 2006. Pages 213–235
 
   
Pedro Trancoso, Kyriakos Stavrou and Paraskevas Evripidou. "DDMCPP: The Data-Driven Multithreading C Pre-Processor". In Proceedings of the Eleventh Annual Workshop on the Interaction between Compilers and Computer Architecture (Interact-11), held in conjunction with the 13th International Symposium on High-Performance Computer Architecture (HPCA-13), Phoeniz, Arizona, February 2007.
 
   
Kyriakos Stavrou, Pedro Trancoso and Paraskevas Evripidou. "Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor". In Proceedings of the 11th Asia-Pacific Computer Systems Architecture Conference (ACSAC 11). (2006).
 
   
Kyriakos Stavrou, Paraskevas Evripidou, and Pedro Trancoso. "DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor". In Proceedings of the 5th International Workshop on Embedded Computer Systems: Architecture, MOdeling and Simulation (SAMOS-V), Samos, Greece, July 2005.
 
   
Kyriakos Stavrou, Pedro Trancoso and Paraskevas Evripidou. “Parallel Execution with Data-Driven Multithreading”. In the Proceedings of the Third International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2007). Pages 115-118
 
   
Samer Arandi, Kyriakos Stavrou, Pedro Trancoso and Paraskevas Evripidou. “DDM-Cell: Data-Driven Multithreading on the Cell Processor”. In the Proceedings of the Third International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2007). Pages 275-278
 
   
Kyriakos Stavrou, Paraskevas Evripidou and Pedro Trancoso. "Programming and Execution for the DDM-CMP System". In the Proceedings of the second International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2006). Pages 137-140
 
   
Kyriakos Stavrou, Paraskevas Evripidou and Pedro Trancoso. "Fitting More Data-Driven Multithreading Cores into the Chip". In the Proceedings of the first International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2005). Pages 83-86
 
    Funding  
   
Research Promotion Foundation, Cyprus. Project titled “DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor – Development and Implementation”, January 2006 – June 2007.
 
   
HiPEAC, European Network of Excellence on High-Performance Embedded Architecture and Compilation. Project titled “CMPs-based network and storage I/O subsystems”, 10/2005 – 10/2006.
 
   
 
  Thermal Aware Scheduling (TAS) on Chip Multiprocessors Top  
    Abstract  
   
Thermal Aware Scheduling aims at improving the thermal characteristics of the Chip Multiprocessor (CMP) via assigning each process on the "thermally" most appropriate core. Each time a new process is to be executed the operating system must select the core on which it will run. Taking into account the "thermal history" of each core enables improving important thermal parameters such as the average temperature, the spatial and temporal gradients of the chip.
 
    Publications  
   
Kyriakos Stavrou and Pedro Trancoso. "Thermal-Aware Scheduling for Future Chip Multiprocessors". In the Proceedings of the EURASIP Journal on Embedded Systems, Special Issue on Embedded Systems for Portable and Mobile Video Platforms. In Press.
 
    Kyriakos Stavrou and Pedro Trancoso. "Thermal-Aware Scheduling: A solution for Future Chip Multiprocessors Thermal Problems". In the Proceedings of 9th Euromicro Conference on Digital System Design  
   
Kyriakos Stavrou and Pedro Trancoso. "Thermal-Aware Scheduling for Chip Multiprocessors". Technical Report TR 05-16, Department of Computer Science, University of Cyprus, November 2005.
 
   
Kyriakos Stavrou and Pedro Trancoso. "TSIC: Thermal Scheduling Simulator for Chip Multiprocessors". In the Proceedings of 10th Panhellenic Conference on Informatics (PCI10). Pages 589-599
 
                                                   
                                  Last Update: 07-09-2007 Webstats4U - Free web site statistics Personal homepage website counter