The Department of Computer Science at the University of Cyprus cordially invites you to the Colloquium entitled:
Future Many-core Processors: Challenges and Solutions
Speaker: Dr. Pedro Trancoso
Processor design has evolved considerably in the last years. In order to cope with Moore's Law, processors became increasingly complex and their power consumption reached unacceptable levels. This led to a paradigm shift to what currently is the de-facto standard the multi-core processors. Even though these processors are able to offer high performance at a lower power consumption level, they introduce new challenges, particularly as the number of cores per processor increases. It is expected that in the future we will have thousands of cores within a chip and that there will be cores of different characteristics on the same chip. Such processors are known as heterogeneous many-core chips. In this presentation an overview of the past, present, and future research projects dealing with these issues will be given. The focus is on two topics: TFlux, an implementation of the Data-Driven Multithreading execution model and the Fine-grain parallelism for different multi-cores and accelerators. In addition, results from different applications and scheduling for the Intel Single-chip Cluster Computer (SCC) 48-core processor will be presented. All projects are unified under a common umbrella: the vision that future heterogeneous many-core processors will be packaged together with a virtualization layer hiding the complexity and managing the resources to exploit the best performance.
Pedro Trancoso is an Assistant Professor at the Department of Computer Science at the University of Cyprus, which he joined in 2002. He has a PhD and MSc. in Computer Science from the University of Illinois at Urbana-Champaign, USA. His research interests are in the area of Computer Architecture and include Multi-core Architectures, Memory Hierarchy, Parallel Processing and Programming Models, Database Workloads, and High-Performance Computing. Currently his research team, Computer Architecture, Systems and Performance Evaluation Research - CASPER (www.cs.ucy.ac.cy/carch/casper) is composed of 5 PhD students (2 of them jointly with colleagues in Spain and Portugal), 1 MSc student, and 5 undergraduate students. The latest funding for his research include the participation in the TERAFLUX EU FP7 IP project (4 years) and the lending of a 48-core experimental processor, the Intel SCC, by the Intel Corporation. He is also a member of the HiPEAC Network of Excellence.
This colloquium is part of the speaker's procedure for evaluation and promotion from Assistant Professor to Associate Professor.
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