The Department of Computer Science at the University of Cyprus cordially invites you to the Colloquium entitled:

Towards Unified Mechanisms for Inter-Processor Communication


Speaker: Prof. Manolis Katevenis
Affiliation: FORTH-ICS and Univ. of Crete, Greece
Category: Colloquium
Location: Room 148, Faculty of Pure and Applied Sciences (FST-01), 1 University Avenue, 2109 Nicosia, Cyprus (directions)
Date: Friday, January 30th, 2009
Time: 09:30 - 10:30 EET
Host: Yiannakis Sazeides (yanos AT

Communication (both interprocessor and I/O), i.e. data movement, is at least as important as computation, especially in multiprocessors. To reduce latency, new architectures will need to bring the supporting hardware, i.e. the network interfaces (NI), close to each processor, hence at the same level as their caches. Both the cache controller and the NI move data, thus they can benefit from being merged together. Implicit communication occurs when we do not know in advance which input data will be needed, or who last modified them; cache coherence works well for such communication. Explicit communication is when the producer knows who the consumers will be, or when the consumer knows its input data set ahead of time. Cache prefetchers or remote DMA (RDMA) are effective transfer mechanisms for explicit communication; however, RDMA uses 3 to 5 times less packets for an equivalent transfer, thus saving a lot of energy. In the SARC project, we are designing CMP nodes where the local SRAM blocks of the processor are configurable as partly-cache and partly-scratchpad memory, and where the cache controller and network interface are merged together, thus unifying the hardware support for implicit and explicit communication.

Short Bio:
Manolis Katevenis received the Ph.D. degree from U.C.Berkeley in 1983 and the ACM Doctoral Dissertation Award in 1984 for his thesis on "Reduced Instruction Set Computer Architectures for VLSI". After a brief term on the faculty of Computer Science at Stanford University, he is in Greece, with the University of Crete and with FORTH, since 1986. After RISC, his research has been on interconnection networks and interprocessor communication. In packet switch architectures, his contributions since 1987 have been mostly in per-flow queueing, credit-based flow control, congestion management, weighted round-robin scheduling, buffered crossbars, and non-blocking switching fabrics. In multiprocessing and clustering, his contributions since 1993 have been on remote-write-based, protected, user-level communication.

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Sponsor: The CS Colloquium Series is supported by a generous donation from Microsoft