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The Department of Computer Science at the University of Cyprus cordially invites you to the Colloquium entitled:

Spatio-Temporal Memory Streaming

 

Speaker: Prof. Babak Falsafi
Affiliation: EPFL, Switzerland.
Category: Colloquium
Location: Room 148, Faculty of Pure and Applied Sciences (FST-01), 1 University Avenue, 2109 Nicosia, Cyprus (directions)
Date: Friday, January 23, 2009
Time: 17:00 - 18:00 EET
Host: Pedro Trancoso (pedro AT cs.ucy.ac.cy)
URL: https://www.cs.ucy.ac.cy/colloquium/index.php#cs.ucy.2009.falsafi

Abstract:
Device scaling in processor fabrication technologies along with microarchitectural innovation have led to a tremendous gap between processor and memory performance. While architects have primarily relied on deeper cache hierarchies to reduce this performance gap, the limited capacity in higher cache levels and simple data placement/eviction policies have resulted in diminishing returns for commercial workloads with large memory footprints and adverse access patterns. Moreover, proposals to bridge the gap using runahead execution or large instruction windows do not benefit workloads with little inherent memory-level parallelism such as transaction processing on databases or web servers. The STeMS (Spatio-Temporal Memory Streaming) project at EPFL is exploring memory system designs that exploit repetitive spatial and temporal correlation among memory accesses and construct memory streams that can be moved and managed together through the memory hierarchy to hide the long access latencies. In this talk, I will present: (a) results from offline trace analysis and cycle-accurate simulation showing that a large fraction of memory accesses in server workloads are spatially and/or temporally correlated, and (b) candidate STeMS architectures to exploit such correlation.

Short Bio:
Babak Falsafi is a Professor in the School of Computer and Communication Sciences at EPFL, and an Adjunct Professor of Electrical and Computer Engineering and Computer Science at Carnegie Mellon. He is the Microarchitecture thrust leader for the FCRP Center for Circuit and System Solutions and directs the Parallel Systems Architecture Laboratory (PARSA) at EPFL. His research targets architectural support for parallel programming, resilient systems, architectures to break the memory wall, and analytic and simulation tools for computer system performance evaluation. In 1999, in collaboration with T. N. Vijaykumar he showed for the first time that multiprocessors do not need relaxed memory consistency models to achieve high performance. He is a recipient of an NSF CAREER award in 2000, IBM Faculty Partnership Awards between 2001 and 2004, and an Alfred P. Sloan Research Fellowship in 2004. He is a senior member of IEEE and ACM.

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Sponsor: The CS Colloquium Series is supported by a generous donation from Microsoft