Paraskevas Evripidou

The TSU is a hardware-based mechanism which provides data-driven synchronization, based on the DSC-model, for conventional microprocessors in a large-scale network of workstations. During program execution, the TSU schedules each thread based on data availability. Scheduling based on data availability provides tolerance to long memory and communications latencies inherent in large-scale multiprocessors, thus making the proposed architecture truly scalable and easily programmed. The TSU also provides for significant performance improvements by independently managing the flow of data to a processing node's cache based on data availability. An overall development goal will be to eliminate cache misses in each of the processing nodes through the use of the TSU design. The TSU design is based on the Decoupled Synchronization Computation (DSC) model of execution developed by the Principal Investigator (PI).The TSU will be built from High-speed, high-density, High I/O count field-programmable gate arrays (FPGA's). This will allow rapid modifications of the TSU during the development phase as the TSU algorithms are translated to hardware and fine tuned.The TSU board will be plug-in board that will fit in the cache-connector that is provided on the PC motherboards.