The research work focuses in the area of Computer Architecture, and more specifically in the following topics: Parallel Processing, Memory Hierarchy, and Database Workloads. The main objective is to study techniques and propose architecture optimizations to exploit the performance offered by future large-scale many-core systems for emerging applications. With the demand for more performance and the advances in technology, we have recently seen a shift in the processor architecture towards multi-core systems. These systems offer a potential for very high performance but also raise many challenges such as thermal management, off-chip memory accesses, and programmability. At the same time, applications are also changing and becoming more demanding on the systems. Having all of the above in mind, we consider the following as the main challenges for future large-scale many-core processors:

  1. Chip Configuration (type of cores, number of cores, internal memory, integrated devices)
  2. Dynamic Management of the Chip (power and thermal management, voltage and frequency regulation)
  3. Out-of-Chip Access (access to memory devices from the cores)
  4. Performance Scalability and Isolation (task scheduling, application speedup and execution of multiple applications)
  5. Programmability (programming models)

It is expected that we will have in the future a large number of heterogeneous cores in a single chip along with other dedicated devices such as memory controllers and accelerators. These systems will be very hard to program, tune, and manage. As such, our vision is that this very powerful architecture will be encapsulated by an abstraction layer that will offer to the programmer the view of a simple traditional multi-core processor but will manage dynamically the resources and take decisions at runtime as to provide the best available performance for the currently executing application(s). It is important that this abstraction layer is: modular as to allow for different managing features to be added; efficient as to add negligible overhead compared to native execution; and transparent to the OS and users. Our vision is that this abstraction layer will be packaged together with the hardware from the processor manufacturer as it will allow the manufacturer to provide a common abstraction to different underlying hardware but exporting the same interface to the users and/or programmers.