Short Bio

Pedro Petersen Moura Trancoso is an Associate Professor at the Department of Computer Science at the University of Cyprus, which he joined in 2002. He has a PhD and MSc. in Computer Science from the University of Illinois at Urbana-Champaign, USA. His research interests are in the area of Computer Architecture and include Multicore Architectures, Memory Hierarchy, Parallel Processing and Programming Models, Database Workloads, High-Performance Computing, Approximate Computing, and Reversible Computing. Currently his research team, Computer Architecture, Systems and Performance Evaluation Research – CASPER is currently composed of 2 PhD students. The latest funding for his research include the participation in the UniServer EU H2020 project (3 years, starting 2/2016), Reversible Computation EU COST (4 years, started 4/2015), TERAFLUX EU FP7 IP project (4 years, completed in 2014) and the lending of a 48-core experimental processor, the Intel SCC, by the Intel Corporation. He is also a member of the IEEE, ACM, and the HiPEAC Network of Excellence.

Publications

Peer reviewed journal articles.

  1. A. Diavastos and P. Trancoso, “SWITCHES: A Lightweight Runtime for Data-flow Execution of Tasks on Many-cores,” ACM TACO, accepted for publication
  2. G. Karakonstantis, D. Gizopoulos, P. Trancoso, Y. Sazeides, C. Antonopoulos, and D Nikolopoulos, “Error-Resilient Server Ecosystems for Exceeding Pessimistic Design Margins,” IEEE Computer, accepted for publication
  3. A. Diavastos, P. Trancoso, M. Lujan, I. Watson, “Integrating Transactions into the Data-Driven Multi-threading Model using the TFlux Platform,” International Journal of Parallel Processing (IJPP) 44(2): 257-277 (2016)
  4. R. Giorgi, R. M. Badia, F. Bodin, A. Cohen, P. Evripidou, P. Faraboschi, B. Fechner, G. R. Gao, A. Garbade, R. Gayatri, S. Girbal, D. Goodman, B. Khan, S. Koliai, J. Landwehr, N. M. Lê, F. Li, M. Luján, A. Mendelson, L. Morin, N. Navarro, T. Patejko, A. Pop, P. Trancoso, T. Ungerer, I. Watson, S. Weis, S. Zuckerman, M. Valero, “TERAFLUX: Harnessing Dataflow in Next Generation Teradevices,” Microprocessors and Microsystems – Embedded Hardware Design 38(8): 976-990 (2014)
  5. C. Cascaval, P. Trancoso, V. K. Prasanna, “Guest Editorial: Computing Frontiers,” International Journal of Parallel Programming 41(3): 355-356 (2013)
  6. H. Franke, P. H. J. Kelly, P. Trancoso, “Guest Editorial: Computing Frontiers,” International Journal of Parallel Programming 40(6): 551-552 (2012)
  7. F. Pratas, P. Trancoso, L. Sousa, A. Stamatakis, G. Shi, V. V. Kindratenko, “Fine-grain parallelism using multi-core, Cell/BE, and GPU Systems,” Parallel Computing 38(8): 365-390 (2012)
  8. V. Kindratenko and P. Trancoso, “Trends in High-Performance Computing,” IEEE Computing in Science and Engineering, Volume 13, Number 3, pp. 92-95, 2011
  9. G. Shi, V. Kindratenko, F. Pratas, P. Trancoso, and M. Gschwind, “Application Acceleration with the Cell Broadband Engine,” IEEE Computing in Science and Engineering, Volume 12, Number 1, pp. 76-81, 2010
  10. J. Aguilar-Saborit, P. Trancoso, V. Muntes-Mulero, and J.L. Larriba-Pey, “Dynamic Adaptive Data Structures for Monitoring Data Streams,” Data & Knowledge Engineering Journal, Elsevier Science, Volume 66, Number 1, pp. 92-115, 2008
  11. K. Tatas, C. Kyriacou, P. Evripidou, P. Trancoso, and S. Wong, “Rapid Prototyping of the Data-Driven Chip-Multiprocessor (D2-CMP) using FPGAs,” Parallel Processing Letter (PPL), Volume 18, Number 2, pp. 291-306, 2008
  12. K. Stavrou, C. Kyriacou, P. Evripidou, and P. Trancoso, “Chip Multiprocessor based on Data-Driven Multithreading Model,” International Journal of High Performance Systems Architecture, Volume 1, Number 1, pp. 34–43, 2007
  13. K. Stavrou and P. Trancoso, “Thermal-Aware Scheduling for Future Chip Multiprocessors,” EURASIP Journal on Embedded Systems, Volume 2007 (2007), Article ID 48926, 15 pages, doi:10.1155/2007/48926
  14. P. Trancoso, “Watt Matters Most? Design Space Exploration of High-Performance Microprocessors for Power-Performance Efficiency,” Journal of Circuits, Systems, and Computers, Volume 16, Number 3, pp. 357-378, 2007
  15. C. Kyriacou, P. Evripidou, and P. Trancoso, “Data-Driven Multithreading Using Conventional Microprocessors,” IEEE Transactions on Parallel and Distributed Systems, Volume 17, Issue 10, pp. 1176–1188, October 2006, ISSN:1045-9219
  16. P. Trancoso, P. Evripidou, K. Stavrou, and C. Kyriacou, “A Case for Chip Multiprocessors based on the Data-Driven Multithreading Model,” International Journal of Parallel Programming, Volume 34, Issue 3, pp. 213–235, June 2006, ISSN:0885-7458
  17. C. Kyriacou, P. Evripidou, and P. Trancoso, “CacheFlow: Cache Optimizations for Data Driven Multithreading,” Parallel Processing Letters, World Scientific, Volume 16, Issue 2, pp. 229-244, June 2006
  18. J. Aguilar-Saborit, P. Trancoso, V. Muntes-Mulero, and J.L. Larriba-Pey, “Dynamic Count Filters,” ACM Sigmod Record, Volume 35, Issue 1, pp. 26–32, March 2006, ISSN:0163-5808

Peer reviewed conference and workshop contributions

  1. A. Diavastos and P. Trancoso, “Auto-tuning Static Schedules for Task Data-flow Applications,” in Proc. of the First Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems (ANDARE’17), Portland, Oregon, USA, September 2017
  2. A. Malek, E. Vasilakis, V. Papaefstathiou, P. Trancoso and I. Sourdis, “Odd-ECC: On-demand DRAM Error Correcting Codes,” in Proc. of the Third International Symposium on Memory Systems (MEMSYS ’17), Washington, U.S.A., October 2017
  3. M. Rimborg, P. Trancoso and G. Carlstedt, “PHOENIX: Efficient Computation in Memory,” in Proc. of the Third International Symposium on Memory Systems (MEMSYS ’17), Washington, U.S.A., October 2017
  4. S. Tzilis, M. Pericas, P. Trancoso, and I. Sourdis “SWAS: Stealing Work using Approximate System-load Information,” in Proc. of the 13th International Workshop on Scheduling and Resource Management for Parallel and Distributed Systems (SRMPDS’17) co-located with ICPP 2017, pp. 1-10, Bristol, UK, August 2017
  5. P. Petrides and P. Trancoso, “Heterogeneous- and NUMA-aware Scheduling for Many-core Architectures”, in Proc. of the 10th ACM International Systems and Storage Conference (SYSTOR 2017), Haifa, Israel, May 2017
  6. M. Otoom, A. Jaleel and P. Trancoso, “Using Personality Metrics to Improve Cache Interference Management in Multicore Processors”, in Proc. of the 14th ACM international Conference on Computing Frontiers (CF ’17), pp. 1-4, Siena, Italy, May 2017
  7. K. Tovletoglou, C. Chalios, G. Karakonstantis, L. Mukhanov, H. Vandierendonck, D. S. Nikolopoulos, P. Koutsovasilis, M. Maroudas, C. Antonopoulos, C. Kalogirou, N. Bellas, S. Lalis, M. M. Rafique, S. Venugopal, A. Prat-Perez, A. Diavastos, Z. Hadjilambrou, P. Nikolaou, Y. Sazeides, P. Trancoso, G. Papadimitriou, M. Kaliorakis, A. Chatzidimitriou and D. Gizopoulos, “An Energy-Efficient and Error-Resilient Server Ecosystem Exceeding Conservative Scaling Limits”, in Proc. of the Energy-efficient Servers for Cloud and Edge Computing 2017 Workshop (ENeSCE 2017), Stockholm, Sweden, co-located with HiPEAC 2017, January 23, 2017
  8. M. Alvanos and P. Trancoso, “Video SIMDBench: Benchmarking the Compiler Vectorization for Multimedia Applications”, in Proc. of the Euromicro Conference on Digital System Design (DSD), pp. 168-175, Limassol, Cyprus, August 2016
  9. P. Trancoso, “Moving to Memoryland: In-Memory Computation for Existing Applications,” in Proc. of the 12th ACM international Conference on Computing Frontiers (CF ’15), pp. 1-6, Ischia, Italy, May 2015
  10. A. Diavastos, G. Stylianou, P. Trancoso, “TFluxSCC: Exploiting Performance on Future Many-Core Systems through Data-Flow,” in Proc. of the 23rd Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP 2015), pp. 190-198, Turku, Finland, March 2015
  11. M. Otoom, P. Trancoso, H. Almasaeid, and M. Alzubaidi, “Scalable and Dynamic Global Power Management for Multicore Chips,” in Proc. of the 6th ACM Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures (PARMA-DITAM ’15), pp. 25-30, Amsterdam, Netherlands, January 2015
  12. A. Diavastos, G. Stylianou, and P. Trancoso, “TFluxSCC: A Case Study for Exploiting Performance in Future Many-core Systems,” in Proc. of the 11th ACM Conference on Computing Frontiers (CF ’14), pp. 1-2, Cagliari, Italy, May 2014
  13. P. Trancoso, “Getting Ready for Approximate Computing: Trading Parallelism for Accuracy for DSS Workloads,” in Proc. of the 11th ACM Conference on Computing Frontiers (CF ’14), pp. 1-10, Cagliari, Italy, May 2014
  14. M. Solinas, R. M. Badia, F. Bodin, A. Cohen, P. Evripidou, P. Faraboschi, B. Fechner, G. R. Gao, A. Garbade, S. Girbal, D. Goodman, B. Khan, S. Koliai, F. Li, M. Luján, L. Morin, A. Mendelson, N. Navarro, A. Pop, P. Trancoso, T. Ungerer, M. Valero, S. Weis, I. Watson, S. Zuckermann, and R. Giorgi, “The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices,” in Proc. of the 2013 IEEE Euromicro Conference on Digital System Design (DSD), pp. 272-279, September 2013
  15. P. Petrides, and P. Trancoso, “Addressing the Challenges of Future Large-Scale Many-core Architectures,” in Proc. of the ACM International Conference on Computing Frontiers (CF ’13), pp. 1-4, Ischia, Italy, May 2013
  16. P. Petrides, A. Diavastos, C. Christofi, and P. Trancoso, “Scalability and Efficiency of Database Queries on Future Many-Core Systems,” in Proc. of the 21st IEEE Euromicro international Conference on Parallel, Distributed, and Network-Based Processing (PDP), pp. 24-28, February 2013
  17. A. Prat-Pérez, D. Dominguez-Sal, J. Larriba-Pey, and P. Trancoso, “Producer-Consumer: The Programming Model for Future Many-core Processors,” in Proc. of the 26th International Conference on Architecture of Computing Systems (ARCS), pp. 110-121, Prague, Czech Republic, February 2013
  18. C. Christofi, G. Michael, P. Trancoso, and P. Evripidou, “Exploring HPC Parallelism with Data-Driven Multithreating,” in Proc. of the 2012 IEEE Data-Flow Execution Models for Extreme Scale Computing Workshop (DFM), pp. 10-17, September 2012
  19. F. Pratas, P. Tomás, P. Trancoso, L. Sousa, “Energy efficient stream-based configurable architecture for embedded platforms,” in Proc. of the International Conference on Embedded Computer Systems: Archi tectures, Modeling and Simulation (SAMOS XII), pp. 193-200, Samos, Greece, July 2012
  20. P. Petrides, G. Nicolaides and P. Trancoso, “HPC Performance Domains on Multi-core Processors with Virtualization” in Proc. of the 25th International Conference on Architecture of Computing Systems (ARCS 2012), pp. 123-134, Munich, Germany, February 2012
  21. A. Diavastos, P. Petrides, G. Falcao and P. Trancoso, “LDPC Decoding on the Intel SCC” in Proc. of 20th Euromicro International Conference on Parallel, Distributed and Network-Based Computing (PDP 2012), pp. 57-65, Garching, Germany, February 2012
  22. A. Diavastos, P. Trancoso, M. Lujan and I. Watson, “Integrating Transactions into the Data-Driven Multi-threading Model using the TFlux Platform” in Proc. of the Data-Flow Execution Models for Extreme Scale Computing (DFM) Workshop, pp. 19-27, Galveston, Texas, U.S.A., October 2011
  23. P. Petrides, A. Diavastos, and P. Trancoso, “Exploring Database Workloads on Future Clustered Many-Core Architectures,” in Proc. of the 3rd Many-core Applications Research Community Symposium (MARC 2011), Ettlingen, Germany, July 2011
  24. P. Trancoso, N. Martinez, and J-L Larriba-Pey, “Memory-, Bandwidth-, and Power-Aware Multi-core for a Graph Database Workload,” in Proc. of the 24th International Conference on Architecture of Computing Systems (ARCS 2011), pp. 171-182, Lake Como, Italy, February 2011
  25. P. Petrides, F. Pratas, L. Sousa, and P. Trancoso, “Virtualization for Morphable Multi-Cores,” in Proc. of the 2nd Workshop on Parallel Programming and
Run-Time Management Techniques for Many-core Architectures (PARMA 2011), Lake Como, Italy, February 2011
  26. F. Pratas, P. Trancoso, A. Stamatakis, and L. Sousa, “Fine-grain Parallelism using Multi-core, Cell/BE, and GPU Systems: Accelerating the Phylogenetic Likelihood Function,” in Proc. of the 38th International Conference on Parallel Processing (ICPP-2009), pp. 9-17, Vienna, Austria, September 2009
  27. K. Stavrou, D. Pavlou, M. Nikolaides, P. Petrides, P. Evripidou, P. Trancoso, Z. Popovic, and R. Giorgi, “Programming Abstractions and Toolchain for Multithreaded Dataflow Architectures,” in Proc. of the 8th International Symposium on Parallel and Distributed Computing (ISPDC’09), pp. 107-114, Lisbon, Portugal, July 2009
  28. P. Trancoso, D. Othonos, A. Artemiou, “Data Parallel Acceleration of Decision Support Queries Using Cell/BE and GPUs,” in Proc. of the 2009 ACM International Conference on Computing Frontiers (CF’2009), pp. 117-126, Ischia, Italy, May 2009
  29. K. Stavrou, D. Pavlou, M. Nicolaides, S. Arandi, P. Evripidou, and P. Trancoso, “TFlux: A Portable Platform for Data-Driven Multithreading on Commodity Multicore Systems,” in Proc. of the 37th Intl Conference on Parallel Processing (ICPP 2008), Portland, U.S.A., pp. 25-34, Sep 2008
  30. M. Pappas, J-L Larriba-Pey, and P. Trancoso, “Categorized Sliding Window in Streaming Data Management Systems,” in Proc. of the 19th International Conference on Database and Expert Systems Applications (DEXA ’08), Turin, Italy, pp. 625-635, Sep 2008
  31. P. Trancoso and A. Artemiou, “Exploring the GPU to Accelerate DSS Query Execution,” in Proc. of the ACM Conference on Computing Frontiers, poster session, Ischia, Italy, pp. 109-110, May 2008.
  32. K. Papadopoulos, K. Stavrou and P. Trancoso, “HelperCoreDB: Exploiting Multicore Technology for Databases,” in Proc. of the 22nd IEEE International Parallel & Distributed Processing Symposium (IPDPS 2008), Miami, USA, pp. 1 – 11, April 2008.
  33. K. Tatas, C. Kyriacou, S. Wong, P. Trancoso, and P. Evripidou, “Rapid Prototyping of the Data-Driven Multithreading Chip-Multiprocessor using FPGAs,” in Proc. of the 2nd HiPEAC Workshop on Reconfigurable Computing, Goteborg, Sweden, January 2008.
  34. K. Papadopoulos, K. Stavrou and P. Trancoso, “HelperCoreDB: Exploiting Multicore Technology for Databases,” in Proc. of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, pp. 420, September 2007.
  35. P. Trancoso, K. Stavrou and P. Evripidou. “DDMCPP: The Data-Driven Multithreading C Pre-Processor,” in Proc. of the Eleventh Annual Workshop on the Interaction between Compilers and Computer Architecture (Interact-11), held in conjunction with the 13th International Symposium on High-Performance Computer Architecture (HPCA-13), Phoeniz, Arizona, February 2007.
  36. K. Stavrou, P. Trancoso and, P. Evripidou, “DDM-CMP Design and Implementation,” in Proc. of the Eleventh Asia-Pacific Computer Systems Architecture Conference (ACSAC 2006), Shangai, China, pp. 244-259, September 2006
  37. H. Vandierendonck and P. Trancoso, “Building and Validating a Reduced TPC-H Benchmark,” in Proc. of the 2006 Conference on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS ’06), pp. 383-392, September 2006
  38. P. Trancoso, “Adaptive High-end Microprocessor for Power-Performance Efficiency,“ in Proc. of the Euromicro Symposium on Digital System Design, Architectures, Methods and Tools (DSD 2006), IEEE Computer Society, pp. 221-228, August 2006
  39. K. Stavrou and P. Trancoso, “Thermal-Aware Scheduling: A solution for Future Chip Multiprocessors Thermal Problems,“ in Proc. of the Euromicro Symposium on Digital System Design, Architectures, Methods and Tools (DSD 2006), IEEE Computer Society, pp. 40, August 2006
  40. K. Stavrou and P. Trancoso, “TSIC: Thermal Scheduling Simulator for Chip Multiprocessors “, in Proc. of the 10th Panhellenic Conference on Informatics (PCI 2005), Springer LNCS, pp. 589-599, November 2005
  41. M. Charalambous, P. Trancoso, and A. Stamatakis, “Initial Experiences Porting a Bioinformatics Application to a Graphics Processor”, in Proc. of the 10th Panhellenic Conference on Informatics (PCI 2005), Springer LNCS, pp. 415-425, November 2005
  42. P. Trancoso, C. Adamou and H. Vandierendonck, “Reducing TPC-H Benchmarking Time” , in Proc. of the 10th Panhellenic Conference on Informatics (PCI 2005), Springer LNCS, pp. 641-650, November 2005
  43. P. Trancoso and M. Charalambous, “Exploring Graphics Processor Performance for General Purpose Applications“, in Proc. of the Euromicro Symposium on Digital System Design, Architectures, Methods and Tools (DSD 2005), IEEE Computer Society, pp. 306-313, August 2005
  44. P. Trancoso, “Dynamic Split: Flexible Border Between Instruction and Data Cache“, in Proc. of the Euromicro Symposium on Digital System Design, Architectures, Methods and Tools (DSD 2005), IEEE Computer Society, pp. 476-483, August 2005
  45. K. Stavrou, P. Evripidou, and P. Trancoso, “DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor” in Proc. of the 5th International Workshop on Embedded Computer Systems: Architecture, MOdeling, and Simulation (SAMOS-V), Springer LNCS 3553, pp. 364-373, July 2005
  46. P. Trancoso, “Design Space Navigation for Neighboring Power-Performance Efficient Microprocessor Configurations” in Proc. of the 18th International Conference on Architecture of Computing Systems, Springer LNCS 3432, pp. 193-206, March 2005
  47. P. Trancoso, “One Size Does Not Fit All: A Case for Heterogeneous Multiprocessor Systems”, in Proc. of the IADIS International Conference Applied Computing 2005, pp. 15-22, February 2005
  48. P. Trancoso, “What to Adapt in a High-Performance Microprocessor” in Proc. of the Euromicro Symposium on Digital System Design, Architectures, Methods and Tools (DSD 2004), IEEE Computer Society, pp. 556-563, August 2004
  49. C. Kyriacou, P. Evripidou, and P. Trancoso, “CacheFlow: A Short-Term Optimal Cache Management Policy for Data Driven Multithreading” in Proc. of the 10th International Euro-Par Conference (Euro-Par 2004), Springer LNCS 3149, pp. 561-570, August 2004
  50. P. Trancoso, “Power-Performance Efficiency Design of a High-Performance Microprocessor for Decision Support Workloads” in Proc. of the Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-7), held in conjunction with the 10th International Symposium on High-Performance Computer Architecture (HPCA-10), pp. 49-56, February 2004
  51. P. Trancoso and N. Angeli, “GridArchSim: Computer Architecture Simulation on the Grid”, in Proc. CD of the 2nd European Across Grids Conference (AxGrids) 2004, 4 pages, January 2004
  52. P. Trancoso, “In-Memory Parallelism for Database Workloads” in Proc. of the 8th International Euro-Par Conference (Euro-Par 2002), Springer LNCS 2400, pp. 532-542, August 2002
  53. P. Trancoso, “eEdu: A Database-Driven Tool for Online Education Material” in Proc. of the 8th Panhellenic Conference on Informatics (EPY-8), pp. 362-371, November 2001
  54. P. Trancoso and J. Torrellas, “Exploiting Intelligent Memory for Database Workloads” in Proc. of the Workshop on Memory Performance Issues (WMPI 2001), held in conjunction with the 28th International Symposium on Computer Architecture (ISCA28), pp. 177-186, June – July, 2001
  55. S. Mylonas, P. Trancoso and M. Trimikliniotis, “Adaptive noise canceling and edge detection in images using PVM on a NOW” in Proc. of the 10th Mediterranean Electrotechnical Conference (MEleCon 2000), pp. 681-684, May 2000
  56. P. Trancoso and J. Torrellas, “Cache Optimization for Memory-Resident Decision Support Commercial Workloads” in Proc. of the International Conference on Computer Design (ICCD’99), IEEE Computer Society, pp. 546-554, October 1999
  57. Q. Cao, P. Trancoso, J-L. Larriba, J. Torrellas, B. Knighten, and Y. Won, “Detailed Characterization of a Quad Pentium Pro Server Running TPC-D” in Proc. of the International Conference on Computer Design (ICCD’99), IEEE Computer Society, pp. 108-115, October 1999
  58. P. Trancoso and J. Torrellas, “Exploiting Caches Under Database Workloads” in Proc. of the First Workshop on Computer Architecture Evaluation using Commercial Workloads, Las Vegas, Nevada, U.S.A., February 1998
  59. P. Trancoso, J.-L Larriba-Pey, Z. Zhang, and J. Torrellas, “The Memory Performance of DSS Commercial Workloads in Shared-Memory Multiprocessors” in Proc. of the Third International Symposium on High-Performance Computer Architecture (HPCA-3), IEEE Computer Society, pp. 250-260, February 1997
  60. P. Trancoso, J.-L Larriba-Pey, Z. Zhang, and J. Torrellas, “The Memory Performance of DSS Commercial Workloads in Shared-Memory Multiprocessors” in Proc. of the Sixth Workshop on Scalable Shared-Memory Multiprocessors, Cambridge, Massachusetts, U.S.A., October 1996
  61. P. Trancoso and J. Torrellas, “The Impact of Speeding up Critical Sections with Data Prefetching and Forwarding” in Proc. of the 1996 International Conference on Parallel Processing (ICPP’96), IEEE Computer Society, pp. 79-86, August 1996
  62. M. Castro, N. Neves, P. Trancoso, and P. Sousa, “MIKE – A distributed object-oriented programming platform on top of the Mach micro-kernel” in Proc. of the USENIX Mach III Symposium, Santa Fe, New Mexico, U.S.A., April 1993

Books or chapter contributions

  1. A. Ilic, F. Pratas, P. Trancoso, and L. Sousa, “High-Performance Computing on Heterogeneous Systems: Database Queries on CPU and GPU, In High Performance Scientific Computing with Special Emphasis on Current Capabilities and Future Perspectives”, IOS Press, April 2011
  2. P. Trancoso and P. Evripidou, “Parallel Computer Architecture” in “Handbook of Parallel Computing and Statistics” E.J. Kontoghiorghes (ed.), pp. 43-73, Chapman & Hall/CRC, Florida, January 2006.
  3. P. Trancoso and J. Torrellas, “Exploiting Intelligent Memory for Database Workloads” in “High Performance Memory Systems” H. Hadimioglu (ed.), pp. 279-292. Springer-Verlag, New York, September 2003.

Reports

  1. P. Petrides, F. Pratas, L. Sousa, P. Trancoso, “Virtualization for Morphable Multi-Cores,” HiPEAC Technical Report, TR-HiPEAC-0013, July 2010
  2. P. Evripidou, P. Trancoso, and C. Kyriakou, “A Case for Data-Driven Multithreading with Conventional Microprocessors”, Technical Report TR-05-9, University of Cyprus, March 2005
  3. C. Kyriakou, P. Evripidou, and P. Trancoso, “Data-Driven Multithreading Using Conventional Microprocessors”, Technical Report TR-05-4, University of Cyprus, March 2005
  4. P. Trancoso, “Optimizing Memory-Resident Decision Support System Workloads for Cache Memories”, Ph.D. Thesis, University of Illinois at Urbana-Champaign, Urbana, Illinois, June 1998 (UIUCDCS-R-98-2053)
  5. P. Trancoso and J. Torrellas, “Cache Optimization for Memory-Resident Decision Support Commercial Workloads”, Technical Report TR-CSRD-1538, University of Illinois at Urbana-Champaign, Urbana, Illinois, June 1998
  6. P. Trancoso, “Performance Optimization Based on Characterizing Synchronization”, Master Thesis, University of Illinois at Urbana-Champaign, Urbana, Illinois, October 1995

Patents

  1. J. Saborit, J-L Larriba-Pey, and P. Trancoso, “Procedure to Efficiently Represent, in time and space, a set of elements that is updated dynamically in time”, filed on 28/07/2005

 

Projects

Funds from the EU

  • [2017] European Union. EuroLab-4-HPC, Collaboration Grant (Andreas Diavastos, UCY), EUR 4.6K. Title: “Efficient Task-based Runtime System: Merging concepts from SWITCHES and TAO”. Role: PI
  • [2016] European Union. H2020-ICT-2015, ICT-04-2015, EUR 4.8M (405K to UCY), 3 years. Title: “UniServer: A Universal Micro-Server Ecosystem by Exceeding the Energy and Performance Scaling Boundaries”. PI: George Karakonstantis, Queens University Belfast, UK. Role: co-PI UCY partner (together with Yannakis Sazeidis)
  • [2015] European Union. ICT COST Action IC1405, 4 years. Title: “Reversible computation – extending horizons of computing”. PI: Irek Ulidowski, Leicester University, UK. Role: MC member
  • [2011] European Union, HiPEAC2 NoE Collaboration Grant (Aamer Jaleel, Intel Massachusetts, Inc., U.S.A.), EUR 7.2K. Title: “Efficient Last-Level Cache Utilization for Many-core Processors”. Role: PI
  • [2011] European Union, HiPEAC2 NoE Collaboration Grant (Arnau Prat, UPC, Barcelona, Spain), EUR 7.0K. Title: “Parallelizing Graph Databases”. Role: PI
  • [2010] European Union. FP7-ICT-2009-4: FET, EUR 7.5M (706K to UCY), 4 years. Title: “TERAFLUX: Exploiting Dataflow Parallelism in Teradevice Computing”. PI: Roberto Giorgi, University of Siena, Italy. Role: co-PI UCY partner (together with Paraskevas Evripidou)
  • [2010] European Union, HiPEAC2 NoE Collaboration Grant (Mikel Lujan, University of Manchester, UK), EUR 2.5K. Title: “Evaluation of Many-Core Architectures using TFlux and TM”. Role: PI
  • [2005] European Union, HiPEAC NoE, EUR 33.7K. Title: “CMPs-based network and storage I/O subsystems”. Role: co-PI
  • [2005] European Union, HPC-Europa Transnational Access Programme, EUR 1.9K. Title: “Database Performance Optimization using Reconfigurable Hardware” (visit to the CEPBA-CESCA Supercomputing Center of the Universitat Politecnica de Barcelona (UPC)). Role: PI
  • [2004] European Union, Network of Excellence CoreGRID, FP6-004265. Title: “European Research Network on Foundations, Software Infrastructures and Applications for Large-Scale Distributed GRID and Peer-to-Peer Technologies”. Role: Member

Funds from local research councils

  • [2010] Research Promotion Foundation, Cyprus, EUR 3.7M. Title: “Cy-Tera: A Multi-Teraflop/s computing facility for Science and Technology in Cyprus”. Role: Helped in the preparation of the proposal. co-PI for the Department of Computer Science of UCY.
  • [2007] Research Promotion Foundation, Cyprus, EUR 25K. Title: “Security in Open Multi-Application SMART CARDS (S-OMA SMART CARDS)”. Role: PI
  • [2006] Research Promotion Foundation, Cyprus, EUR 60K. Title: “Efficient System for Weather Prediction using Graphics Processors”. Role: PI
  • [2006] Research Promotion Foundation, Cyprus, EUR 130K. Title: “DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor – Development and Implementation”. Role: co-PI

Funds from industry

  • [2016] Intel Corporation, Intel Hardware Accelerator Research Program, remote access to Intel Xeon+FPGA systems (Broadwell + Arria10) as well as licenses for proprietary software tools and access to relevant workshops. Title: “Exploiting heterogeneous reconfigurable systems for (i) domain-specific languages and programming models, (ii) cache coherency issues, and (iii) reliability enabling mechanisms for continuous operation and graceful degradation”. Role: co-PI
  • [2015] Maxeler Technologies, Maxeler University Program (MAX-UP), licenses to proprietary software and access to remote systems. Title: “Query Evaluation with Maxeler Dataflow Computing”. Role: PI
  • [2010] Intel Corporation, Many-core Applications Research Community, SCC Research Proposal, loan of a research prototype processor – 48-core Intel SCC System. Title: “TFlux SCC”. Role: PI

Teaching

Undergraduate (Bachelor)

  • CS427 Parallel Processing: Architectures and Programming Languages, 7.0 ECTS, 2008
  • CS421 Computer Architecture, bachelor, 7.0 ECTS, 2006
  • CS372 Parallel Processing, 7.5 ECTS, 2012, 2010
  • CS370 Computer Architecture, 7.5 ECTS, 2015, 2010, 2008
  • CS323 Compilers, 7.5 ECTS, 2016, 2015, 2014, 2013, 2012, 2011, 2010, 2009, 2008, 2007
  • CS221 Computer Organization, 7.5 ECTS, 2013, 2012
  • CS132 Programming Principles II, 7.5 ECTS, 2015, 2013

Postgraduate (Masters and Doctorate)

  • CS655 Advanced Parallel Processing, 8.0 ECTS, 2015, 2013, 2011, 2009, 2007
  • CS605 Advanced Computer Architecture, 8.0 ECTS, 2014, 2011, 2009, 2007

 

 

News

Paper accepted at ANDARE’17

Our work with title “Auto-tuning Static Schedules for Task Data-flow Applications” has been accepted for publication and presentation at the First Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems (ANDARE’17), Portland, Oregon, USA, September 2017  (co-located with PACT 2017)

Paper accepted at DSD 2017

Our work with title “Low-cost Sub-5W Processors for Edge HPC” has been accepted for publication and presentation at the 20th Euromicro Conference on Digital System Design (DSD 2017), Vienna, Austria, August-September 2017.

Papers accepted at MEMSYS 2017

Our works with title “Odd-ECC: On-demand DRAM Error Correcting Codes” and “PHOENIX: Efficient Computation in Memory” have been accepted for publication and presentation at the Third International Symposium on Memory Systems (MEMSYS 2017), Washington DC, USA, October 2017.