- Data-Driven execution of the Tile LU Decomposition (pdf)
- Tree-based read-only data-chunks for NVRAM programming (pdf)
- CnC: A Dependence Programming Mode (pdf)
George Matheou (University of Cyprus), Costas Kyriacou (Frederick University) and Paraskevas Evripidou (University of Cyprus)
Kumud Bhandari (Rice Unviversity) and Vivek Sarkar (Rice Unviversity)
Zoran Budimlic (Rice University) and Kathleen Knobe (Rice University)
- Challenges and Opportunities for Dataflow Processing
on Exascale Computers (pdf)
Justin M. Wozniak (University of Chicago and Argonne National Laboratory), Michael Wilde (University of Chicago and Argonne National Laboratory) and Ian T. Foster (University of Chicago and Argonne National Laboratory)
The International workshop on “Data-Flow Models (DFM) for extreme scale computing” was held in six consecutive years in conjunction with the PACT conference. The purpose of DFM continues being to bring together those researchers interested in novel computational models based on Data-Flow principles of execution. The switch to multi-core systems has raised concurrency to the level of a major issue if we are to use the increasing number of cores in a chip.
In the past five decades, sequential computing dominated the computer architecture landscape because designers were successful at building faster and faster computers by solely relying on improvements on fabrication technologies and architectural/organization optimizations. The most severe limitation of the sequential model, namely its inability to tolerate long memory latencies has slowed down the performance gains. This phenomenon is the ubiquitous Memory Wall. While various mechanisms have been implemented to overcome the wall (such as extremely efficient hardware prefetch support for example), they only add to another wall that hampers highly efficient execution of programs and modern chip design: the Power Wall. Power considerations and heat dissipation issues have forced manufacturers to switch to multiple cores per chip and thus move into the concurrency era.
New concurrent models/paradigms are needed in order to fully utilize the potential of multi-core chips. The data-flow model is a formal model that can handle concurrency and tolerate memory and synchronization latencies. Data-Flow inspired systems could also be simpler and more power efficient than conventional systems.
Recent work has shown that the data-flow principles can be used to develop systems that can outperform systems based on conventional techniques. Thus, it is time to revisit data-driven computation and bring it to the multi-core and extreme scale computing.
DFM 2016 solicits novel papers that include but are not limited to:
- Novel Data-Flow inspired Execution models and architectures
- Functional and Single assignment based Languages.
- Strict and non-strict execution models.
- Compilers and tools for Data-Flow/Data-Driven systems.
- Hybrid Data-driven/Control-driven systems.
- Position Papers on the Future of Data-Flow in the Multi-core era and beyond.
- All accepted papers will appear in the Computer Society Digital Library
July 24, 2016
August 28, 2016
DFM 2016 will accept both Full (8 pages) and Short papers (4 pages). Papers should be prepared using the IEEE Proceedings format; Short Papers could be submitted in the form of extended abstracts. All accepted papers will appear in the Computer Society Digital Library. Submission site https://easychair.org/conferences/?conf=dfm2016