4th Workshop on Design for Reliability Workshop scope: While technology is scaling well into the nanometer era, design of reliable, dependable and verifiable systems emerges as one of the most prominent design challenges. The increasing rate of intermittent and permanent faults due to design errors, device variability and manufacturing defects (including wear-outs), environmental impact and aging of devices (degradation) rises significantly as device size and power supply voltage shrink. Process variation also shifts the traditional deterministic design methodology towards a more stochastic and unorthodox design paradigm. The increased design complexity, increased device parameter variations due to manufacturing and lithographic defects, reduced noise margins resulting from the power supply voltage reduction, and the increase of noise due to crosstalk and power supply, all call for a design environment where traditional design methodologies are no longer effective. These cause further challenges in completing design verification and manufacturing tests; such effects manifest as inherent unreliability of the components, redefining the design and test paradigm for next-generation computing systems. Additionally, energy reduction and performance enhancement techniques force designs to run near zero margins, and factors which cannot be controlled such as soft errors, thermal impact and aging result in an increased occurrence of transient and hard faults in computing systems. Topics of interest include: * Dependable systems from unreliable components, lifelong reliability * Fault-Tolerant micro-architectures and system architectures * Testing and verification strategies for the future * On-line (dynamic) testing and verification techniques * Software-based methodologies for fault tolerance and testing * System validation mechanisms * Built-in self diagnosis, self-tuning and recovery schemes * Self-adaptive systems * System-level design and integration for reliability, verifiability and dependability * Error modeling, detection, correction, and tolerance for transient and permanent errors * Reliable on-chip communications * Energy/reliability/performance tradeoffs * Aggressive power saving mechanisms * Compiler/architecture/OS methodologies and strategies for reliability Call for Papers: Two types of papers are invited: - Technical papers, maximum 10 pages (LNCS Format), for relatively mature ideas. - Position papers, maximum 4 pages (LNCS Format), for research and development directives. Submission Process - Website, TBA. Tentative Schedule: Paper Submission: October 31, 2011 - EXTENDED SUBMISSION DEADLINE to November 7, 2011 Author Notification: December 5, 2011 Camera-Ready Paper due: December 29, 2011 Technical Program Committee: Christiana Bolchini (Politecnico di Milano) Luigi Carro (UFRGS, Brazil) Kypros Constantinides (Microsoft) Anand Dixit (Oracle) Oguz Ergin (University of Economics and Technology, Turkey) Said Hamdioui (Delft University of Technology) Dimitris Gizopoulos (University of Athens) Wunderlich Hans-Joachim (Universitat Stuttgart) Maria K. Michael (University of Cyprus) Marco Ottavi (University of Rome "Tor Vergata") Emre Ozer (ARM) Ozcan Ozturk (Bilkent University, Turkey) Yiannakis Sazeides (University of Cyprus) Vilas Sridharan (AMD) Theocharis Theocharides (University of Cyprus) Osman Unsal (BSC) Xavi Vera (Intel) Workshop Organizers: Yiannakis Sazeides (University of Cyprus) Theocharis Theocharides (University of Cyprus) Maria K. Michael (University of Cyprus) Webchair: Marios Kleanthous (University of Cyprus)